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31篇 您的检索式：作者名="Reviriego P"

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	题名	作者	年代	出处	被引量
1	Performance evaluation of energy efficient Ethernet显示文摘	REVIRIEGO P HERNANDEZ J A LARRABEITI D	2009	IEEE Communications Letters2009，13，9：	1
2	Reliability of single-error correction protected memories 显示文摘	MAESTRO J A REVIRIEGO P	2009	IEEE TransReliab2009，58，1：	1
3	Study of the effects of multi bit error correction codes on the reliability of memories in the presence of MBUs 显示文摘	REVIRIEGO P MAESTRO J A	2009	IEEE Trans Dev & Mater Reliab2009，9，1：	1
4	Study of the potential energy savings in Ethemet by combining energy efficient Ethernet and adaptive link rate显示文摘	REVIRIEGO P MAESTRO J A HERNANDEZ J A	2012	European Transactions on Emerging Telecommunication Technologies2012，23，：	1
5	Reliability analysis of memories suffering multiple bit upsets 显示文摘	REVIRIEGO P MAESTRO J A CERVANTES C	2008	IEEE Trans Dev : Mater Reliab2008，7，4：	1
6	A fast and efficient technique to apply selective TMR through optimization显示文摘	Ruano O Maestro J A and Reviriego P	2011	Microelectronics Reliability2011，51，12：	1
7	Six-month effectiveness and tolerability of pioglitazone in combination with sulfonylureas or metformin for the treatment of type 2 diabetes mellitus显示文摘	Rodriguez A Reviriego J Polavieja P	2008	Med Clin2008，131，：	1
8	Reliability Analysis of Memories Suffering Multiple Bit Upsets显示文摘	Reviriego P Maestro J A		0，，04：	1
9	Reliability of single error correction protected memories显示文摘	Maestro J Reviriego A P	2009	IEEE Trans Nucl Sci2009，58，1：	1
10	Efficient arithmetic-residue-based SEU-tolerant FIR filter design 显示文摘	GAO Z REVIRIEGO P PAN W	2013	IEEE Transactions on Circuits and Systems II: Express Briefs2013，60，8：	1
11	Study of the effects of multibit error correction codes on the reliability of memories in the presence of MBUs显示文摘	Reviriego P Maestro J A	2009	IEEE Transactions on Device and Materials Reliability2009，9，1：	1
12	Efficient arithmetic residue-based SEU tolerant FIR filter design显示文摘	GAO Z REVIRIEGO P PAN W	2013	Circuits&Systems II Express Briefs IEEE Transactions on2013，60，8：	1
13	Efficient majority logic fault detection with difference-det codes for mem- ory applications显示文摘	Liu S-F Reviriego P Maestro J A	2012	IEEE Transactions on Very Large Scale Integration (VLSI) Systems2012，20，1：	1
14	Reliability analysis of memories suffering multiple bit upsets显示文摘	Reviriego P Maestro J A Cervantes C	2007	Device and Materials Reliability IEEE Transactions on2007，7，4：	1
15	Error de- tection in majority logic decoding of euclidean geometry low density parity check (EG-LDPC) codes显示文摘	Reviriego P Maestro J A Flanagan M F	2013	IEEE Transactions on Very Large Scale Integration (VLSI) Systems2013，21，1：	1
16	Signal shaping dual modular redundancy for soft error tolerant finite impulse response filters显示文摘	REVIRIEGO P BLEAKLEY C J MAESTRO J A	2011	Electronics Letters2011，47，23：	1
17	Energy efficiency in industrial Ethernet:the case of Powerlink显示文摘	Maestro J Reviriego P		0，，08：	1
18	Reliability of single-error correction protected memories显示文摘	MAESTRO J A REVIRIEGO P	2009	IEEE Transactions on Reliability2009，58，1：	1
19	Reliability analysis of memories suffering multiple bit upsets显示文摘	REVIRIEGO P MAESTRO J A	2007	IEEE Trans on Device and Materials Reliability2007，7，4：	1
20	Improved glycadmic control without increased risk of hypoglycaemia with a 25% insulin/Iispro75% NPL mixture twice daily compared with NPH twice daily in patients with type2 diabetes显示文摘	Reviriego J Herz M Roach P	2004	J Appl Ther Res2004，4，6：	1

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