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22篇 您的检索式:作者名="Reviriego A P"
    题名 作者 年代 出处 被引量
1Performance evaluation of energy efficient Ethernet显示文摘REVIRIEGO P HERNANDEZ J A LARRABEITI D 2009IEEE Communications Letters2009,13,9:1
2Reliability of single-error correction protected memories 显示文摘MAESTRO J A REVIRIEGO P 2009IEEE TransReliab2009,58,1:1
3Study of the effects of multi bit error correction codes on the reliability of memories in the presence of MBUs 显示文摘REVIRIEGO P MAESTRO J A 2009IEEE Trans Dev & Mater Reliab2009,9,1:1
4Study of the potential energy savings in Ethemet by combining energy efficient Ethernet and adaptive link rate显示文摘REVIRIEGO P MAESTRO J A HERNANDEZ J A 2012European Transactions on Emerging Telecommunication Technologies2012,23,:1
5Reliability analysis of memories suffering multiple bit upsets 显示文摘REVIRIEGO P MAESTRO J A CERVANTES C 2008IEEE Trans Dev : Mater Reliab2008,7,4:1
6A fast and efficient technique to apply selective TMR through optimization显示文摘Ruano O Maestro J A and Reviriego P 2011Microelectronics Reliability2011,51,12:1
7Six-month effectiveness and tolerability of pioglitazone in combination with sulfonylureas or metformin for the treatment of type 2 diabetes mellitus显示文摘Rodriguez A Reviriego J Polavieja P 2008Med Clin2008,131,:1
8Reliability Analysis of Memories Suffering Multiple Bit Upsets显示文摘Reviriego P Maestro J A 0,,04:1
9Reliability of single error correction protected memories显示文摘Maestro J Reviriego A P 2009IEEE Trans Nucl Sci2009,58,1:1
10Study of the effects of multibit error correction codes on the reliability of memories in the presence of MBUs显示文摘Reviriego P Maestro J A 2009IEEE Transactions on Device and Materials Reliability2009,9,1:1
11Efficient majority logic fault detection with difference-det codes for mem- ory applications显示文摘Liu S-F Reviriego P Maestro J A 2012IEEE Transactions on Very Large Scale Integration (VLSI) Systems2012,20,1:1
12Reliability analysis of memories suffering multiple bit upsets显示文摘Reviriego P Maestro J A Cervantes C 2007Device and Materials Reliability IEEE Transactions on2007,7,4:1
13Error de- tection in majority logic decoding of euclidean geometry low density parity check (EG-LDPC) codes显示文摘Reviriego P Maestro J A Flanagan M F 2013IEEE Transactions on Very Large Scale Integration (VLSI) Systems2013,21,1:1
14Signal shaping dual modular redundancy for soft error tolerant finite impulse response filters显示文摘REVIRIEGO P BLEAKLEY C J MAESTRO J A 2011Electronics Letters2011,47,23:1
15Reliability of single-error correction protected memories显示文摘MAESTRO J A REVIRIEGO P 2009IEEE Transactions on Reliability2009,58,1:1
16Reliability analysis of memories suffering multiple bit upsets显示文摘REVIRIEGO P MAESTRO J A 2007IEEE Trans on Device and Materials Reliability2007,7,4:1
17Efficient error detection codes ibr multiple-bit upset correction in SRAMs with BICS 显示文摘Reviriego P Maestro J A 2009ACM Transactions on Design Automation of Electronic Systems2009,14,1:1
18Reliability analysis ofmemories suffering multiple bit upsets 显示文摘Reviriego P Maestro J A Cervantes C 2007IEEE Transactionson Device and Materials Reliability2007,7,4:1
19Reliability Analysis of Memories Suffer- ing Multiple Bit Upsets 显示文摘Reviriego P Maestro J A 2007IEEE Trans on Device and Materials Reliability2007,7,4:1
20Error de- tection in majority logic decoding of euclidean geometry low density parity check codes 显示文摘REVIRIEGO P MAESTRO J A FLANAGAN M F 2013IEEE Transactions on VLSI2013,30,1:1
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