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	题名	作者	年代	出处	被引量
1	Characterization and testing of physical failures in MOS logic circuits显示文摘	Banerjee P Abraham J	1984	IEEE Design and Test of Computers1984，1，8：	3
2	A Model and Methodology for Hardware-software Codesign显示文摘	Donald E T Jay K A Herman S	1993	IEEE Design & Test of Computers1993，10，3：	2
3	Inductive fault analysis of MOS integrated circuits显示文摘	Shen J Maly W Ferguson F	1985	IEEE Design and Test of Computers1985，2，12：	2
4	lntra-Task Voltage Scheduling for Low-Energy Hard Real-Time Applieations显示文摘	Shin D Kim J Lee S	2001	IEEE Design and Test of Computers2001，18，2：	1
5	Fast template placement for reconfigurable computing systems显示文摘	Bazargan K Kastner R Sarrafzadeh M	2000	IEEE Design and Test of Computers2000，7，1：	1
6	Dynamic Power Management in wireless sensor networks显示文摘	Sinha A Chandrakasan A Mic C	2001	IEEE Design & Test of computers2001，18，2：	1
7	Your Core- My Problem? Integration and Verification of IP显示文摘	Anderson T	2001	IEEE Design & Test2001，18，5：	1
8	Xmas: quick formal modeling of communication fabrics to enable verification显示文摘	CHATTERJEE S KISHINEVSKY M OGRAS U	2012	Design Test of Computers IEEE2012，29，3：	1
9	Dynamic power management in wireless sensor network显示文摘	Sinhua A Chandrakasan A	2001	IEEE Design and Test of Computer2001，18，2：	1
10	The Thereal Network on Chip: Concepts, Architectures, and Implementations显示文摘	Goossens K Dielissen J Radulescu A	2005	IEEE Design and Test of Computers2005，22，5：	1
11	Survey of Test Vector Compression Techniques 显示文摘	Touba N	2006	IEEE Design & Test of Computers2006，23，4：	1
12	Compiler De sign Issues for Embedded Processors 显示文摘	Leupers R	2002	IEEE Design and Test of Computers2002，19，4：	1
13	Vision for Embedded Systems: Platform- Based Design and Software Methodocosy显示文摘	Martin G A	2001	IEEE Design and Test of Conpulers2001，18，6：	1
14	Scan Bist: A multifrequence scan-based BIST method 显示文摘	Nadeau-Dostie B Burek D Hassan A	1994	IEEE Design & Test on Computer1994，11，1：	1
15	High-level modeling and design of asynchronous interface logic显示文摘	A V Yakovlev A M Koelmans L Lavagno	1995	IEEE Design and Test of Computers1995，1995，：	1
16	Dag-map: graph-based FPGA technology mapping for delay optimization 显示文摘	Chen K C Cong J Ding Y	1992	IEEE Design & Test of Computers1992，9，3：	1
17	Incremental verification with error detection, diagnosis, and visualization显示文摘	CHANG K H PAPA D MARKOV I	2009	Design Test of Computers IEEE2009，26，2：	1
18	Dynamic power management in wireless sensor networks显示文摘	] SINHA A CHANDRAKASAN A	2001	IEEE Design & Test of Computers2001，18，2：	1
19	Hardware-software cosynthesis for microcontrollers显示文摘	Ernst R Henkel J Benner T	1993	IEEE Design & Test of Computers1993，10，4：	1
20	Dynamic power management in wireless sensor networks 显示文摘	SINHA A CHANDRAKASAN A	2001	IEEE Design and Test of Computers2001，18，2：	1

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