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10篇 您的检索式：作者名="Pramod Kumar Meher"

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		题名	作者	年代	出处	被引量
	1	Fault-Tolerant Bit-Parallel Multiplier for Polynomial Basis of GF(2^m)显示文摘Novel fault-tolerant architectures forbit-parallel polynomial basis multiplier over GF(2m),which can correct the erroneous outputs using linearcode, are presented. A parity prediction circuit based onthe code generator polynomial that leads lower space overhead has been designed. For bit-parallel architectures, the space overhead is about 11%.Moreover, there is only marginal time overhead due toincorporation of error-correction capability thatamounts to 3.5% in case of the bit-parallel multiplier.Unlike the existing concurrent error correction (CEC)multipliers or triple modular redundancy (TMR)techniques for single error correction, the proposed architectures have multiple error-correcting capabilities.	Chiou-Yng Lee Pramod Kumar Meher Chia-Chen Fan	2009	Journal of Electronic Science and Technology of China2009，7，4：	2
	2	Neural-Network-Based Robust Linearization and Compensation Technique for Sensors under Nonlinear Environmental Influences 显示文摘	Jagdish Chandra Patra Goutam Chakraborty Pramod Kumar Meher	2008	IEEE Transactions on Circuits and Systems2008，55，5：	1
	3	FP- GA Realization of FIR Filters by Efficient and Flexible Systoliza- tion Using Distributed Arithmetic 显示文摘	MEHER Pramod Kumar CHANDRASEKARAN Shrutisagar	2008	IEEE Transactions on Signal Processing2008，56，7：	1
	4	CORDIC designs for fixed angle of rotation显示文摘	Pramod Kumar Meher SangYoon Park	2013	IEEE transactions on very large scale integration(VLSI) systems2013，21，2：	1
	5	LUT optimization for memory-based computation 显示文摘	Pramod Kumar Meher	2010	IEEE Transactions on Circuits and Systems II2010，57，4：	1
	6	FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic 显示文摘	MEHER PRAMOD KUMAR CHANDRASEKARAN SHRUTISAGAR AMIRA ABBES	2008	IEEE Transactions on Signal Processing2008，56，71：	1
	7	New approach to Look-UP-Table design and memory-based realization of FIR digital filter显示文摘	Pramod Kumar Meher		0，，03：	1
	8	Memeory efficient modular VLSI architecture for high throughput and low-latency implementation of multilevel lifting 2-D DWT 显示文摘	Mohanty B K Pramod Kumar Meher	2011	IEEE Transactions on Signal Processing2011，59，5：	1
	9	High Throughput Pipelined Realization of Adaptive FIR Filter Based on Distributed Arithmetic 显示文摘	Pramod Kumar Meher Sang Yoon Park	2013	IEEE Transactions on VLSI and System-on-Chip2013，60，6：	1
	10	LUT optimization for memorybased computation显示文摘	Pramod Kumar Meher	2010	IEEE Transaction on Circuits and System2010，57，4：	1

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