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| 1 | A 15 Gbps-NRZ, 30 Gbps-PAM4, 120 mA laser diode driver implemented in 0.15-μm GaAs E-mode pHEMT technology显示文摘This paper presents the design and testing of a 15 Gbps non-return-to-zero(NRZ),30 Gbps 4-level pulse amplitude modulation(PAM4)configurable laser diode driver(LDD)implemented in 0.15-μm GaAs E-mode pHEMT technology.The driver bandwidth is enhanced by utilizing cross-coupled neutralization capacitors across the output stage.The output transmission-line back-termination,which absorbs signal reflections from the imperfectly matched load,is performed passively with on-chip 50-Ωresistors.The proposed 30 Gbps PAM4 LDD is implemented by combining two 15 Gbps-NRZ LDDs,as the high and low amplification paths,to generate PAM4 output current signal with levels of 0,40,80,and 120 mA when driving 25-Ωlasers.The high and low amplification paths can be used separately or simultaneously as a 15 Gbps-NRZ LDD.The measurement results show clear output eye diagrams at speeds of up to 15 and 30 Gbps for the NRZ and PAM4 drivers,respectively.At a maximum output current of 120 mA,the driver consumes 1.228 W from a single supply voltage of-5.2 V.The proposed driver shows a high current driving capability with a better output power to power dissipation ratio,which makes it suitable for driving high current distributed feedback(DFB)lasers.The chip occupies a total area of 0.7×1.3 mm^(2). | Ahmed Wahba Lin Cheng Fujiang Lin | 2021 | Journal of Semiconductors2021，42，7： | 2 |
| 2 | A 0.5–3.0 GHz SP4T RF switch with improved body self-biasing technique in 130-nm SOI CMOS显示文摘A single-pole four-throw(SP4T)RF switch with charge-pump-based controller is designed and implemented in a commercial 130-nm silicon-on-insulator(SOI)CMOS process.An improved body self-biasing technique based on diodes is utilized to simplify the controlling circuitry and improve the linearity.A multistack field-effect-transistor(FET)structure with body floating technique is employed to provide good power-handling capability.The proposed design demonstrates a measured input 0.1-d B compression point of 38.5 d Bm at 1.9 GHz,an insertion loss of 0.27 d B/0.33 d B and an isolation of 35 d B/27 d B at 900 MHz/1.9 GHz,respectively.The overall chip area is only 0.49 mm^2.This RF switch can be used in GSM/WCDMA/LTE frontend modules. | Hao Zhang Qiangsheng Cui Xu Yan Jiahui Shi Fujiang Lin | 2020 | Journal of Semiconductors2020，41，10： | 1 |
| 3 | Production of double-stranded RNA for interference with TMV infection utilizing a bacterial prokaryotic expression system显示文摘 | Guohua Yin Zhaonan Sun Nan Liu Lin Zhang Yunzhi Song Changxiang Zhu Fujiang Wen | 2009 | Applied Microbiology and Biotechnology2009，，2： | 1 |
| 4 | SiGe HBTs Model Converting Technique From SGP to VBIC Model显示文摘 | Lin Fujiang Zhou Tianshu Chen Bo | 2002 | Microelectronics Journal2002，33，： | 1 |
| 5 | SiGe HBTs Model Converting Technique from SGP to VBIC Model显示文摘 | Lin Fujiang Zhou Tianshu | 2002 | Microelectronics Journal2002，，2002： | 1 |
| 6 | Production of double-stranded RNA for interference with TMV infection utilizing a bacterial prokaryotic expression system显示文摘 | Guohua Yin Zhaonan Sun Nan Liu Lin Zhang Yunzhi Song Changxiang Zhu Fujiang Wen | 2009 | Applied Microbiology and Biotechnology2009，，2： | 1 |
| 7 | On the design of high-speed energy-efficient successive-approximation logic for asynchronous SAR ADCs显示文摘This paper analyzes the power consumption and delay mechanisms of the successive-approximation(SA) logic of a typical asynchronous SAR ADC,and provides strategies to reduce both of them.Following these strategies,a unique direct-pass SA logic is proposed based on a full-swing once-triggered DFF and a self-locking tri-state gate.The unnecessary internal switching power of a typical TSPC DFF,which is commonly used in the SA logic,is avoided.The delay of the ready detector as well as the sequencer is removed from the critical path.A prototype SAR ADC based on the proposed SA logic is fabricated in 130 nm CMOS.It achieves a peak SNDR of 56.3 dB at 1.2 V supply and 65 MS/s sampling rate,and has a total power consumption of 555 μW,while the digital part consumes only 203 μW. | Jiaqi Yang Ting Li Mingyuan Yu Shuangshuang Zhang Fujiang Lin Lin He | 2017 | Journal of Semiconductors2017，38，8： | 0 |
| 8 | Analytical model of non-uniform charge distribution within the gated region of GaN HEMTs显示文摘A physics-based analytical expression that predicts the charge,electrical field and potential distributions along the gated region of the GaN HEMT channel has been developed.Unlike the gradual channel approximation(GCA),the proposed model considers the non-uniform variation of the concentration under the gated region as a function of terminal applied volt-ages.In addition,the model can capture the influence of mobility and channel temperature on the charge distribution trend.The comparison with the hydrodynamic(HD)numerical simulation showed a high agreement of the proposed model with numerical data for different bias conditions considering the self-heating and quantization of the electron concentration.The ana-lytical nature of the model allows us to reduce the computational and time cost of the simulation.Also,it can be used as a core expression to develop a complete physics-based transistorⅣmodel without GCA limitation. | Amgad A.Al-Saman Eugeny A.Ryndin Xinchuan Zhang Yi Pei Fujiang Lin | 2023 | Journal of Semiconductors2023，44，8： | 0 |
| 9 | Design and analysis of an energy-efficient O-QPSK coherent IR-UWB transceiver with a 0.52° RMS phase-noise fractional synthesizer显示文摘This paper explores an energy-efficient pulsed ultra-wideband(UWB) radio-frequency(RF) front-end chip fabricated in 0.18-μm CMOS technology, including a transmitter, receiver, and fractional synthesizer. The transmitter adopts a digital offset quadrature phase-shift keying(O-QPSK) modulator and passive direct-phase multiplexing technology, which are energy-and hardware-efficient, to enhance the data rate for a given spectrum.A passive mixer and a capacitor cross-coupled(CCC) source-follower driving amplifier(DA) are also designed for the transmitter to further reduce the low power consumption. For the receiver, a power-aware low-noise amplifier(LNA) and a quadrature mixer are applied. The LNA adopts a CCC boost common-gate amplifier as the input stage, and its current is reused for the second stage to save power. The mixer uses a shared amplification stage for the following passive IQ mixer. Phase noise suppression of the phase-locked loop(PLL) is achieved by utilizing an even-harmonics-nulled series-coupled quadrature oscillator(QVCO) and an in-band noise-aware charge pump(CP) design. The transceiver achieves a measured data rate of 0.8 Gbps with power consumption of 16 m W and31.5 m W for the transmitter and the receiver, respectively. The optimized integrated phase noise of the PLL is0.52° at 4.025 GHz. | Yutong Ying Fujiang Lin Xuefei Bai | 2018 | Journal of Semiconductors2018，39，3： | 0 |
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