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290篇 您的检索式：期刊名="IEEE Trans VLSI"

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	题名	作者	年代	出处	被引量
1	Transformation and re-synthesis for testability of RT-Level control data path specification 显示文摘	Bhattacharya S	1993	IEEE Trans VLSI1993，1，3：	1
2	High-level synthesis of recoverable VLSI microarchitectures显示文摘	D M Blough F J Kurdahi Seong Yong Ohm	1999	IEEE Trans on VLSI Systems1999，7，4：	1
3	A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains显示文摘	APPERSON R W YU Z Y MEEUWSEN M J	2007	IEEE Trans VLSI Syst2007，15，10：	1
4	Low power digital systems based on adiabatic switching principles显示文摘	Svensson L Koller J	1994	IEEE Trans VLSI Systems1994，2，4：	1
5	Complex shaped on-wafer interconnects modeling for CMOS RFICs显示文摘	SHI X K YEO S MA J G	2008	IEEE Trans VLSI Syst2008，16，7：	1
6	Predictive system shutdown and other architectural techniques for energy efficient programmable computation显示文摘	Srivastava M Chandrakasan A Brodersen R	1996	IEEE Trans VLSI Systems1996，4，1：	1
7	A survey of design techniques for system-level dynamic power management 显示文摘	Benini L Bogliolo A Micheli G D	2000	IEEE Trans on Very Large Scale Integration (VLSI) Systems2000，8，3：	1
8	Predictive system shutdown and other architectural techniques for energy efficient programmable computation 显示文摘	Srivastava M B Chandrakasan A P Brodersen R W	1996	IEEE Trans on Very Large Scale Integration (VLSI) Systems1996，4，1：	1
9	The effect of LUT and cluster size on deep Submicron FPGA performance and density 显示文摘	Ahmed E Rose J	2004	IEEE Trans Very Large Scale Integration (VLSI)Systems2004，12，3：	1
10	True single-phase adiabatic circuitry显示文摘	Papaefthymioun M C	2001	IEEE Trans VLSI Systems2001，9，1：	1
11	Predictive system shutdown and other architectural techniques for energy efficient programmable computation 显示文摘	SRIVASTAVA M CHANDRAKASAN A BRODERSEN R	1996	IEEE Trans on VLSI Systems1996，，1：	1
12	Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding显示文摘	Lin C H Chen C Y Wu A Y	2011	IEEE Trans on VLSI Systems2011，19，2：	1
13	A survey of power estimation techniques in VLSI circuits显示文摘	F N Najm	1994	IEEE Trans on VLSI Systems1994，2，4：	1
14	A reconfigurable VLSI coprocessing system for the block matching algorithm显示文摘	Yang W	1997	IEEE Trans VLSI Syst1997，5，3：	1
15	A Monte-Carlo approach for power estimation显示文摘	R Burch F Najm	1993	IEEE Trans on VLSI Systems1993，1，1：	1
16	Using magnetic RAM to build low power and soft error-resilient L1 cache 显示文摘	Sun Hongbin Liu Chuanyin Xu Wei	2012	IEEE Trans on Very Large Scale Integration (VLSI) Systems2012，20，1：	1
17	Analysis and design of a low-voltage low-power double-tTail comparator 显示文摘	BABAYAN-MASHHADI S LOTFI R	2014	IEEE Trans VLSI Syst2014，22，2：	1
18	A Fully Pipelined Architecture for The LOCO-I Compression Algrithm显示文摘	Merlino P Abramo A	2009	IEEE Trans on Very Large Scale Integration (VLSI) Systems2009，17，7：	1
19	System design for pixel-parallel image processing 显示文摘	Herrmann F P Hsu L T	1996	IEEE Trans VLSI Syst1996，4，1：	1
20	An on-chip march pattern generator for testing embedded memory cores显示文摘	WANG Wei-Lun LEE Kuen-Jong WANG Jging-Fa	2001	IEEE Trans on VLSI Systems2001，9，5：	1

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