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	题名	作者	年代	出处	被引量
1	A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains显示文摘	APPERSON R W YU Z Y MEEUWSEN M J	2007	IEEE Trans VLSI Syst2007，15，10：	1
2	Complex shaped on-wafer interconnects modeling for CMOS RFICs显示文摘	SHI X K YEO S MA J G	2008	IEEE Trans VLSI Syst2008，16，7：	1
3	A reconfigurable VLSI coprocessing system for the block matching algorithm显示文摘	Yang W	1997	IEEE Trans VLSI Syst1997，5，3：	1
4	Analysis and design of a low-voltage low-power double-tTail comparator 显示文摘	BABAYAN-MASHHADI S LOTFI R	2014	IEEE Trans VLSI Syst2014，22，2：	1
5	System design for pixel-parallel image processing 显示文摘	Herrmann F P Hsu L T	1996	IEEE Trans VLSI Syst1996，4，1：	1
6	Stochastic physical synthesis considering prerouting interconnect uncertainty and process variation for FPGAs显示文摘	LIN Y HE L HUTTON M	2008	IEEE Trans VLSI Syst2008，16，2：	1
7	A CORDIC processor for FFT computation and its implementation using gallium arsenide technology显示文摘	Sarmiento R	1998	IEEE Trans VLSI Syst1998，6，1：	1
8	Design of a low-voltage low-dropout regulator显示文摘	HUANG C H MA Y T LIAO W C	2014	IEEE Trans VLSI Syst2014，22，6：	1
9	A novel wavelet transform-based transient current analysis for fault detection and localization显示文摘	BHUNIA S ROY K	2005	IEEE Trans VLSI Syst2005，13，4：	1
10	Simultaneous switch noise in on-chip CMOS distribution networks 显示文摘	TANG K-T FRIEDMAN E-G	2002	IEEE Trans VLSI Syst2002，10，4：	1
11	Low power encoding for ultra low power design显示文摘	Stan M R Burlesson W P	1997	IEEE Trans VLSI Syst1997，5，4：	1
12	Error-resilient motion estimation architecture显示文摘	VARATKAR G V SHANBHAG N R	2008	IEEE Trans VLSI Syst2008，16，10：	1
13	Equivalent circuit model of on-wafer CMOS interconnects for RFICs显示文摘	Shi X-M Ma J-G Yeo K S	2005	IEEE Trans VLSI Syst2005，13，9：	1
14	A survey of design techniques for system-level dynamic power management显示文摘	Benini L	2000	IEEE Trans VLSI Syst2000，8，3：	1
15	Asub-1 V- 26 btW low output impedance bandgap reference with a low dropout or source follower mode 显示文摘	NGDCW KWONGDKK WONGN	2011	IEEE Trans VLSI Syst2011，19，7：	1
16	System-on-chip test scheduling with reconfigurable core wrappers 显示文摘	ERIK L HIDEO F	2006	IEEE Trans VLSI Syst2006，14，3：	1
17	Ant colony system application to macrocell overlap removal显示文摘	S Katkoori	2004	IEEE Trans on Very Large Scale Integr (VLSI) Syst2004，12，10：	1
18	Predictive system shutdown and other architectural techniques for energy efficient programmable computation 显示文摘	Srivastava M Chandrakasan A Brodersen R	1996	IEEE Trans VLSI Syst1996，4，：	1
19	Figures of merit to characterize the importance of on-chip induc tance 显示文摘	Friedman E G Neves J L	1999	IEEE Trans VLSI Syst1999，7，4：	1
20	Low-power memory mapping through reducing address bus activity显示文摘	Panda P R Dutt N D	1999	IEEE Trans Very Large Seale(VLSI)Integr Syst1999，7，：	1

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