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| 1 | Reliability evaluation of high-performance,low-power FinFET standard cells based on mixed RBB/FBB technique显示文摘With shrinking transistor feature size,the fin-type field-effect transistor(FinFET) has become the most promising option in low-power circuit design due to its superior capability to suppress leakage.To support the VLSI digital system flow based on logic synthesis,we have designed an optimized high-performance low-power FinFET standard cell library based on employing the mixed FBB/RBB technique in the existing stacked structure of each cell.This paper presents the reliability evaluation of the optimized cells under process and operating environment variations based on Monte Carlo analysis.The variations are modelled with Gaussian distribution of the device parameters and 10000 sweeps are conducted in the simulation to obtain the statistical properties of the worst-case delay and input-dependent leakage for each cell.For comparison,a set of non-optimal cells that adopt the same topology without employing the mixed biasing technique is also generated.Experimental results show that the optimized cells achieve standard deviation reduction of 39.1%and 30.7%at most in worst-case delay and inputdependent leakage respectively while the normalized deviation shrinking in worst-case delay and input-dependent leakage canbe up to 98.37%and 24.13%,respectively,which demonstrates that our optimized cells are less sensitive to variability and exhibit more reliability. | Tian Wang Xiaoxin Cui Yewen Ni Kai Liao Nan Liao Dunshan Yu Xiaole Cui | 2017 | Journal of Semiconductors2017，38，4： | 0 |
| 2 | Ultralow-power high-speed flip-flop based on multimode Fin FETs显示文摘In this paper, we first reconstruct a novel planar static contention-free single-phase-clocked flipflop(S2CFF) based on high-performance fin-type field-effect transistors(FinF ETs) to achieve high speed and ultralow power consumption. Benefiting from better control of the conductive channel, the shorted-gate(SGmode) FinF ET flip-flop obtains a persistent reduction of 56.7% in average power consumption as well as a considerable improvement in timing performance at a typical 10% data switching activity, while the low-power(LP-mode) FinF ET flip-flop promotes the power reduction to 61.8% without appreciable degradation in speed.However, through further analysis of the simulation results, we have revealed an unnecessary energy loss caused by the redundant leaps of internal nodes at the static input ‘0', which has a noticeable negative impact on total power consumption at low data switching activity. In order to overcome this defect, a conditional precharge technique is introduced to control the charging path, and we demonstrate that the independent-gate(IG-mode)FinF ET is the best option for the added control transistor. The verification results indicate that our optimization reduces the power consumption by more than 50% at low data switching activity with an acceptable area and setup time penalty compared with that of LP-mode FinF ET flip-flop. | Kai LIAO Xiaoxin CUI Nan LIAO Tian WANG Dunshan YU Xiaole CUI | 2016 | Science China(Information Sciences)2016，59，4： | 0 |
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