维普期刊资源整合服务平台（V6.5）

维普中文期刊产品整合服务

1篇 您的检索式：作者名="Wang Pengjun Yu Junjun"

选中清除导出查看参考文献查看引证文献引用追踪共1页首页上一页第1页下一页末页 /1 跳转

		题名	作者	年代	出处	被引量
	1	DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT显示文摘First the research is conducted on the design of the two-phase sinusoidal power clock gen- erator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks—Clocked Transmission Gate Adiabatic Logic (CTGAL) circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor (NMOS) and Complementary Metal Oxide Semiconductor (CMOS) latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company (TSMC) 0.25μm CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic (BCRL) and Pass-transistor Adiabatic Logic (PAL) including their clock generators is simulated. The simula-tion result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.	Wang Pengjun Yu Junjun	2007	Journal of Electronics(China)2007，24，2：	5

返回顶部每页显示：

共1页首页上一页第1页下一页末页 /1 跳转

goolge学术搜索-维普

网站首页 | 关于我们 | 联系我们 | 产品服务 | 客服中心 | 广告服务 | 版权声明 | 网站联盟 | 友情链接 | 售卡网点

版权所有© 渝B2-20050021-1　渝公网安备 50019002500403号　违法和不良信息举报中心

互联网出版许可证新出网证(渝)字10号全国400电话 - 免长途话费