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| 1 | Design of a DTCTGAL circuit and its application显示文摘By research on the switch-signal theory for multiple-valued logic circuits,the theory of three essential elements and the principle of adiabatic circuits,a design scheme for a double power clock ternary clocked transmission gate adiabatic logic (DTCTGAL) circuit is presented.The energy injection and recovery can be conducted by the bootstrapped NMOSFET,which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output.An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme.Finally,using the parameters of a TSMC 0.25μm CMOS device,PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics. | 汪鹏君 李昆鹏 梅凤娜 | 2009 | Journal of Semiconductors2009，30，11： | 3 |
| 2 | 具有预计算功能的新型绝热数值比较器设计显示文摘该文通过对钟控传输门绝热逻辑(Clocked Transmission Gate Adiabatic Logic,CTGAL)电路和数值比较器电路工作原理及结构的研究,提出了一种基于CTGAL电路的具有预计算功能的新型绝热数值比较器设计方案。该方案具有冗余抑制作用,将其与利用PAL-2N电路设计的低功耗绝热数值比较器相比,功耗节省平均约60%。PSPCIE模拟结果表明,此数值比较器逻辑功能正确,低功耗特性明显。 | 汪鹏君 曾小旁 | 2010 | 电子与信息学报2010，32，1： | 1 |
| 3 | DESIGN OF TERNARY COUNTER BASED ON ADIABATIC DOMINO CIRCUIT显示文摘By researching the ternary counter and low power circuit design method, a novel design of low power ternary Domino counter on switch-level is proposed. Firstly, the switch-level structure expression of ternary loop operation circuit with enable pin is derived according to the switch-signal theory, and the one bit ternary counter is obtained combining the ternary adiabatic Domino literal operation circuit and buffer. Then the switch-level structure expression of enable signal circuit is derived, and the four bits ternary counter is obtained by cascade connection. Finally, the circuit is simulated by Spice tool and the output waveforms transform in proper order indicating that the logic function is correct. The energy consumption of the four bits ternary adiabatic Domino counter is 63% less than the conventional Domino counterpart. | Yang Qiankun Wang Pengjun Zheng Xuesong | 2013 | Journal of Electronics(China)2013，30，1： | 1 |
| 4 | Design of adiabatic two's complement multiplier-accumulator based on CTGAL显示文摘We propose a new design scheme for a Booth encoder based on clocked transmission gate adiabatic logic(CTGAL). In the new design the structural complexity of the Booth encoder is reduced while the speed of the multiplier is improved. The adiabatic two's complement multiplier-accumulator(MAC) is furthermore a design based on the CTGAL. The computer simulation results indicate that the designed circuit has the correct logic function and remarkably less energy consumption compared to that of the MAC based on complementary metal oxide semiconductor(CMOS) logic. | Peng-jun WANG Jian XU Shi-yan YING | 2009 | Journal of Zhejiang University-Science A(Applied Physics & Engineering)2009，10，2： | 0 |
| 5 | 基于CTGAL电路的低功耗十进制复位计数器设计显示文摘通过对计数器和钟控传输门绝热逻辑电路工作原理及结构的研究,提出一种带复位功能的低功耗十进制计数器设计方案.新方案利用CTGAL电路钟控传输门对输入信号进行采样,然后通过自举操作的NMOS管和CMOS-latch结构对输出负载进行全绝热方式充放电,并通过计数器预置复位端结构实现进制可变计数器的设计.PSPICE的模拟结果表明:所设计的电路具有正确的逻辑功能,在相同工作频率下,与传统CMOS电路实现的十进制计数器相比,平均节省能耗约82%. | 高虹 汪鹏君 | 2009 | 宁波大学学报(理工版)2009，22，4： | 0 |
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