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| 1 | Hetero-gate-dielectric double gate junctionless transistor(HGJLT)with reduced band-to-band tunnelling effects in subthreshold regime显示文摘We propose a hetero-gate-dielectric double gate junctionless transistor(HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling(BTBT) in the sub-threshold region. A junctionless transistor(JLT) is turned off by the depletion of carriers in the highly doped thin channel(device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel.These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor(n–p–n BJT for channel JLT) in the lateral direction by the source(emitter), channel(base) and drain(collector) regions in JLT structure in off-state.The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability. | Bahniman Ghosh Partha Mondal M.W.Akram Punyasloka Bal Akshay Kumar Salimath | 2014 | Journal of Semiconductors2014，35，6： | 2 |
| 2 | Analog performance of double gate junctionless tunnel field effect transistor显示文摘For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor(DG-JLTFET) and the results are compared with the conventional n-type double gate tunnel field effect transistor(DG-TFET) counterpart. Using extensive device simulations, the two devices are compared with the following analog performance parameters, namely transconductance, output conductance, output resistance,intrinsic gain, total gate capacitance and unity gain frequency. From the device simulation results, DG-JLTFET is found to have significantly better analog performance as compared to DG-TFET. | M.W.Akram Bahniman Ghosh | 2014 | Journal of Semiconductors2014，35，7： | 2 |
| 3 | P-type double gate junctionless tunnel field effect transistor显示文摘We have investigated the 20 nm p-type double gate junctionless tunnel field effect transistor(PDGJLTFET) and the impact of variation of different device parameters on the performance parameters of the P-DGJLTFET is discussed. We achieved excellent results of different performance parameters by taking the optimized device parameters of the P-DGJLTFET. Together with a high-k dielectric material(TiO2/ of 20 nm gate length, the simulation results of the P-DGJLTFET show excellent characteristics with a high ION of 0.3 mA/ m,a low IOFF of 30 fA/ m, a high ION=IOFF ratio of 1 1010, a subthreshold slope(SS) point of 23 mV/decade,and an average SS of 49 mV/decade at a supply voltage of –1 V and at room temperature, which indicates that PDGJLTFET is a promising candidate for sub-22 nm technology nodes in the implementation of integrated circuits. | M.W.Akram Bahniman Ghosh Punyasloka Bal Partha Mondal | 2014 | Journal of Semiconductors2014，35，1： | 0 |
| 4 | A laterally graded junctionless transistor显示文摘This paper proposes a laterally graded junctionless transistor taking peak doping concentration near the source and drain region, and a gradual decrease in doping concentration towards the center of the channel to improve the I OFF and I ON/I OFF ratio. The decrease of doping concentration in the lateral direction of the channel region depletes a greater number of charge carriers compared to the uniformly doped channel in the OFF-state,which in turn suppresses the OFF state current flowing through the device without greatly affecting the ON state current. | Punyasloka Bal Bahniman Ghosh Partha Mondal M.W.Akram | 2014 | Journal of Semiconductors2014，35，3： | 0 |
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