2篇
您的检索式：作者名="Jimson Mathew"
|
|
|
题名
|
作者
|
年代
|
出处
|
被引量
|
| 1 | EMD-Att-LSTM: A Data-driven Strategy Combined with Deep Learning for Short-term Load Forecasting显示文摘Electric load forecasting is an efficient tool for system planning, and consequently, building sustainable power systems. However, achieving desirable performance is difficult owing to the irregular, nonstationary, nonlinear, and noisy nature of the observed data. Therefore, a new attention-based encoderdecoder model is proposed, called empirical mode decomposition-attention-long short-term memory(EMD-Att-LSTM).EMD is a data-driven technique used for the decomposition of complex series into subsequent simpler series. It explores the inherent properties of data to obtain the components such as trend and seasonality. Neural network architecture driven by deep learning uses the idea of a fine-grained attention mechanism, that is, considering the hidden state instead of the hidden state vectors, which can help reflect the significance and contributions of each hidden state dimension. In addition, it is useful for locating and concentrating the relevant temporary data,leading to a distinctly interpretable network. To evaluate the proposed model, we use the repository dataset of Australian energy market operator(AEMO). The proposed architecture provides superior empirical results compared with other advanced models. It is explored using the indices of root mean square error(RMSE) and mean absolute percentage error(MAPE). | Neeraj Jimson Mathew Ranjan Kumar Behera | 2022 | Journal of Modern Power Systems and Clean Energy2022，10，5： | 2 |
| 2 | Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2^m)显示文摘An error tolerant hardware efficient verylarge scale integration (VLSI) architecture for bitparallel systolic multiplication over dual base, which canbe pipelined, is presented. Since this architecture has thefeatures of regularity, modularity and unidirectionaldata flow, this structure is well suited to VLSIimplementations. The length of the largest delay pathand area of this architecture are less compared to the bitparallel systolic multiplication architectures reportedearlier. The architecture is implemented using Austria Micro System's 0.35 μm CMOS (complementary metaloxide semiconductor) technology. This architecture canalso operate over both the dual-base and polynomialbase. | Ashutosh Kumar Singh Asish Bera Hafizur Rahaman Jimson Mathew Dhiraj K.Pradhan | 2009 | Journal of Electronic Science and Technology of China2009，7，4： | 0 |
您所在的机构暂未开通此部分的功能，请联系管理员