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| 1 | A Model-Driven Design Framework for Massively Parallel Embedded Systems显示文摘 | Abdoulaye Gamatié Sébastien Le Beux éric Piel Rabie Ben Atitallah Anne Etien Philippe Marquet Jean-Luc Dekeyser | 2011 | ACM Transactions on Embedded Computing Systems (TECS)2011，，4： | 1 |
| 2 | An Optimized SW/HW AVMF Design Based on High-Level Synthesis Flow for Color Images显示文摘In this paper,a software/hardware High-level Synthesis(HLS)design is proposed to compute the Adaptive Vector Median Filter(AVMF)in realtime.In fact,this filter is known by its excellent impulsive noise suppression and chromaticity conservation.The software(SW)study of this filter demonstrates that its implementation is too complex.The purpose of this work is to study the impact of using an HLS tool to design ideal floating-point and optimized fixed-point hardware(HW)architectures for the AVMF filter using square root function(ideal HW)and ROM memory(optimized HW),respectively,to select the best HLS architectures and to design an efficient HLS software/hardware(SW/HW)embedded AVMF design to achieve a trade-off between the processing time,power consumption and hardware cost.For that purpose,some approximations using ROM memory were proposed to perform the square root and develop a fixed-point AVMF algorithm.After that,the best solution generated for each HLS design was integrated in the SW/HW environment and evaluated under ZC702 FPGA platform.The experimental results showed a reduction of about 65%and 98%in both the power consumption and processing time for the ideal SW/HW implementation relative to the ideal SW implementation for an AVMF filter with the same image quality,respectively.Moreover,the power consumption and processing time of the optimized SW/HW are 70%and 97%less than the optimized SW implementation,respectively.In addition,the Look Up Table(LUTs)percentage,power consumption and processing time used by the optimized SW/HW design are improved by nearly 45%,18%and 61%compared the ideal SW/HW design,respectively,with slight decrease in the image quality. | Turki MAlanazi Ahmed Ben Atitallah Imen Abid | 2021 | Computers, Materials & Continua2021，，9： | 0 |
| 3 | Unified FPGA Design for the HEVC Dequantization and Inverse Transform Modules显示文摘As the newest standard,the High Efficiency Video Coding(HEVC)is specially designed to minimize the bitrate for video data transfer and to support High Definition(HD)and ULTRA HD video resolutions at the cost of increasing computational complexity relative to earlier standards like the H.264.Therefore,real-time video decoding with HEVC decoder becomes a challenging task.However,the Dequantization and Inverse Transform(DE/IT)are one of the computationally intensive modules in the HEVC decoder which are used to reconstruct the residual block.Thus,in this paper,a unified hardware architecture is proposed to implement the HEVC DE/IT module for all Transform Unit(TU)block size,including 4×4,8×8,16×16 and 32×32.This architecture is designed using the High-Level Synthesis(HLS)and the Low-Level Synthesis(LLS)methods in order to compare and determine the best method to implement in real-time the DE/IT module.In fact,the C/C++programming language is used to generate an optimized hardware design for DE/IT module through the Xilinx Vivado HLS tool.On the other hand,the LLS hardware architecture is designed by the VHSIC Hardware Description language(VHDL)and using the pipeline technique to decrease the processing time.The experimental results on the Xilinx XC7Z020 FPGA show that the LLS design increases the throughput in term of frame rate by 80%relative to HLS design with a 4.4%increase in the number of Look-Up Tables(LUTs).Compared with existing related works in literature,the proposed architectures demonstrate significant advantages in hardware cost and performance improvement. | Turki M.Alanazi Ahmed Ben Atitallah | 2022 | Computers, Materials & Continua2022，，6： | 0 |
| 4 | An Efficient HW/SW Design for Text Extraction from Complex Color Image显示文摘In the context of constructing an embedded system to help visually impaired people to interpret text,in this paper,an efficient High-level synthesis(HLS)Hardware/Software(HW/SW)design for text extraction using the Gamma Correction Method(GCM)is proposed.Indeed,the GCM is a common method used to extract text from a complex color image and video.The purpose of this work is to study the complexity of the GCM method on Xilinx ZCU102 FPGA board and to propose a HW implementation as Intellectual Property(IP)block of the critical blocks in this method using HLS flow with taking account the quality of the text extraction.This IP is integrated and connected to the ARM Cortex-A53 as coprocessor in HW/SW codesign context.The experimental results show that theHLS HW/SW implementation of the GCM method on ZCU102 FPGA board allows a reduction in processing time by about 89%compared to the SW implementation.This result is given for the same potency and strength of SW implementation for the text extraction. | Mohamed Amin Ben Atitallah Rostom Kachouri Ahmed Ben Atitallah Hassene Mnif | 2022 | Computers, Materials & Continua2022，，6： | 0 |
| 5 | An FPGA Design for Real-Time Image Denoising显示文摘The increasing use of images in miscellaneous applications such as medical image analysis and visual quality inspection has led to growing interest in image processing.However,images are often contaminated with noise which may corrupt any of the following image processing steps.Therefore,noise filtering is often a necessary preprocessing step for the most image processing applications.Thus,in this paper an optimized field-programmable gate array(FPGA)design is proposed to implement the adaptive vector directional distance filter(AVDDF)in hardware/software(HW/SW)codesign context for removing noise from the images in real-time.For that,the high-level synthesis(HLS)flow is used through the Xilinx Vivado HLS tool to reduce the design complexity of the HW part.The SW part is developed based on C/C++programming language and executed on an advanced reduced instruction set computer(RISC)machines(ARM)Cortex-A53 processor.The communication between the SW and HW parts is achieved using the advanced extensible Interface stream(AXI-stream)interface to increase the data bandwidth.The experiment results on the Xilinx ZCU102 FPGA board show an improvement in processing time of the AVDDF filter by 98%for the HW/SW implementation relative to the SW implementation.This result is given for the same quality of image between the HW/SW and SW implementations in terms of the normalized color difference(NCD)and the peak signal to noise ratio(PSNR). | Ahmed Ben Atitallah | 2022 | Computer Systems Science & Engineering2022，43，11： | 0 |
| 6 | An Efficient Text Recognition System from Complex Color Image for Helping the Visually Impaired Persons显示文摘The challenge faced by the visually impaired persons in their day-today lives is to interpret text from documents.In this context,to help these people,the objective of this work is to develop an efficient text recognition system that allows the isolation,the extraction,and the recognition of text in the case of documents having a textured background,a degraded aspect of colors,and of poor quality,and to synthesize it into speech.This system basically consists of three algorithms:a text localization and detection algorithm based on mathematical morphology method(MMM);a text extraction algorithm based on the gamma correction method(GCM);and an optical character recognition(OCR)algorithm for text recognition.A detailed complexity study of the different blocks of this text recognition system has been realized.Following this study,an acceleration of the GCM algorithm(AGCM)is proposed.The AGCM algorithm has reduced the complexity in the text recognition system by 70%and kept the same quality of text recognition as that of the original method.To assist visually impaired persons,a graphical interface of the entire text recognition chain has been developed,allowing the capture of images from a camera,rapid and intuitive visualization of the recognized text from this image,and text-to-speech synthesis.Our text recognition system provides an improvement of 6.8%for the recognition rate and 7.6%for the F-measure relative to GCM and AGCM algorithms. | Ahmed Ben Atitallah Mohamed Amin Ben Atitallah Yahia Said Mohammed Albekairi Anis Boudabous Turki MAlanazi Khaled Kaaniche Mohamed Atri | 2023 | Computer Systems Science & Engineering2023，46，7： | 0 |
| 7 | Managerial Overconfidence and Debt Decisions显示文摘 | Ben Atitallah Rihab Ben Jedidia Lotfi | 2016 | Journal of Modern Accounting and Auditing2016，12，4： | 0 |
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