共被期刊论文引用了3次
您的检索式：您选中1篇文献正在查看引证文献汇总
|
|
|
题名
|
作者
|
年代
|
出处
|
被引量
|
| 1 | 90nm CMOS工艺下3×V_(DD)容限静电检测电路显示文摘提出一种90nm 1.2VCMOS工艺下只用低压器件的新型3×VDD容限的静电检测电路.该电路利用纳米工艺MOSFET的栅极泄漏特性和反馈技术来控制触发晶体管并进而开启箝位器件(可控硅整流器),同时采用多级叠加结构以承受高电压应力.在静电放电时,该电路能产生38mA的触发电流.在3×VDD电压下工作时,每个器件都处于安全电压范围,在25℃时漏电流仅为52nA.仿真结果表明,该检测电路可成功用于3×VDD容限的接口缓冲器. | 杨兆年 刘红侠 朱嘉 | 2015 | 西安电子科技大学学报2015，42，1： | 1 |
| 2 | A single-photon fault-detection method for nanocircuits that use GaN material显示文摘As the complexity of nanocircuits continues to increase,developing tests for them becomes more difficult.Failure analysis and the localization of internal test points within nanocircuits are already more difficult than for conventional integrated circuits.In this paper,a new method of testing for faults in nanocircuits is presented that uses single-photon detection to locate failed components(or failed signal lines)by utilizing the infrared photon emission characteristics of circuits.The emitted photons,which can carry information about circuit structure,can aid the understanding of circuit properties and locating faults.In this paper,in order to enhance the strength of emitted photons from circuit components,test vectors are designed for circuits’components or signal lines.These test vectors can cause components to produce signal transitions or switching behaviors according to their positions,thereby increasing the strength of the emitted photons.A multiple-valued decision diagram(MDD),in the form of a directed acrylic graph,is used to produce the test vectors.After an MDD corresponding to a circuit is constructed,the test vectors are generated by searching for specific paths in the MDD of that circuit.Experimental results show that many types of faults such as stuck-at faults,bridging faults,crosstalk faults,and others,can be detected with this method. | PAN ZhongLiang CHEN Ling ZHANG GuangZhao WU PeiHeng | 2014 | Science China(Technological Sciences)2014，57，2： | 1 |
| 3 | 外延厚度对CMOS倒相器闩锁特性的影响研究显示文摘CMOS电路由于寄生结构的影响,在大电流的情况下,易发生闩锁效应。如有该效应发生,极有可能导致芯片烧毁。一般从电路设计和版图设计两个方面可以减少闩锁效应的产生,同时在工艺方面采取措施可进一步降低闩锁效应,采用外延厚度的控制是比较有效的方式之一。通过外延技术降低衬底寄生电阻Rp的阻值,保证在大电流的情况下,减少寄生三极管导通概率,从而减少闩锁效应的发生。通过仿真验证,明确了外延厚度与CMOS倒相器闩锁特性的关系,获得了外延厚度的最佳值,在极限情况下,外延1.5μm CMOS倒相器抗闩锁能力比30μm外延高8.3倍左右。 | 邵红 | 2017 | 微处理机2017，38，5： | 0 |
您所在的机构暂未开通此部分的功能，请联系管理员