共被期刊论文引用了4次
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| 1 | Novel N-hit single event transient mitigation technique via open guard transistor in 65 nm bulk CMOS process显示文摘In this paper,we proposed a new n-channel MOS single event transient(SET) mitigation technique,which is called the open guard transistor(OGT) technique.This hardening scheme is compared with several classical n-channel MOS hardening structures through 3-D TCAD simulations.The results show that this scheme presents about 35% improvements over the unhardened scheme for mitigating the SET pulse,and its upgrade,the 2-fringe scheme,takes on even more than 50% improvements over the unhardened one.This makes significant sense for the semi-conductor device reliability. | HUANG PengCheng CHEN ShuMing CHEN JianJun LIU BiWei | 2013 | Science China(Technological Sciences)2013，56，2： | 5 |
| 2 | Flip-flops soft error rate evaluation approach considering internal single-event transient显示文摘The internal single-event transient(SET) induced upset in flip-flops is becoming significant with the increase of the operating frequency. However, the conventional soft error rate(SER) evaluation approach could only produce an approximate upset prediction result caused by the internal SET. In this paper, we propose an improved SER evaluation approach based on Monte Carlo simulation. A novel SET-based upset model is implemented in the proposed evaluation approach to accurately predict upsets caused by the internal SET. A test chip was fabricated in a commercial 65 nm bulk process to validate the accuracy of the improved SER evaluation approach. The predicted single-event upset cross-sections are consistent with the experimental data. | SONG RuiQiang CHEN ShuMing HE YiBai DU YanKang | 2015 | Science China(Information Sciences)2015，58，6： | 3 |
| 3 | Analyzing and mitigating the internal single-event transient in radiation hardened flip-flops at circuit-level显示文摘Internal SET has become a great concern in normal radiation-hardened flip-flops with increases in frequency.We investigate the internal SET problem in the traditional hardened flip-flops in this article.We also propose a novel structure to eliminate the internal SET problem.Three-dimensional technology computer-aided design(TCAD)was adopted to verify the hardened performance of this proposed novel structure.Besides,the power and setup time were compared with the traditional hardened flip-flops. | LIANG Bin SONG RuiQiang | 2014 | Science China(Technological Sciences)2014，57，9： | 2 |
| 4 | P型阱接触布局对于单粒子瞬态脉冲宽度的影响显示文摘针对40 nm体硅双阱工艺CMOS(complementary metal oxide semiconductor)反相器的单粒子瞬态敏感效应(single event transient,SET),通过3维TCAD(technology computer aided design)仿真软件模拟计算,研究了P阱接触面积对于单粒子敏感性的影响。仿真结果表明,重离子轰击N型有源区时,增大P阱接触面积可稳定器件的电势和减小双极放大效应,有效减小SET脉冲宽度;重离子轰击P型有源区时,器件受到多种效应影响,增大P阱接触面积虽能减小双极放大效应,但会产生强内建电场,加剧载流子漂移收集,导致SET脉冲宽度增加。此外,阱接触与晶体管的距离对SET脉冲宽度也有一定影响。研究结果表明,增大阱接触与晶体管之间的距离一定程度上可减小SET脉冲宽度,但在轰击P型有源区的情况下,增大阱接触与晶体管之间的距离反而会增大SET脉冲宽度。传统的加固手段对P型阱接触也有较好的作用,但在特定情况下会起到反作用。 | 陈南心 丁李利 陈伟 王坦 张凤祁 徐静妍 罗尹虹 | 2023 | 现代应用物理2023，14，3： | 0 |
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