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| 1 | 基于多相滤波的高速滤波器FPGA设计显示文摘针对吉赫兹数据率实时滤波处理的工程化难题,在传统的多相抽取滤波器基础上进行数学推导,提出一种基于多相滤波的高速滤波器FPGA简便设计方法。该方法在输出数据率不变的前提下,通过多相滤波降低了运算速率,并且实现架构统一,无需额外资源开销,便于模块化设计。仿真结果验证了其可行性。 | 孙健 韩文俊 凌元 | 2018 | 遥测遥控2018，39，5： | 8 |
| 2 | Hardware Architecture of Polyphase Filter Banks Performing Embedded Resampling for Software-Defined Radio Front-Ends显示文摘In this paper, we describe resource-efficient hardware architectures for software-defined radio (SDR) front-ends. These architectures are made efficient by using a polyphase channelizer that performs arbitrary sample rate changes, frequency selection, and bandwidth control. We discuss area, time, and power optimization for field programmable gate array (FPGA) based architectures in an M -path polyphase filter bank with modified N -path polyphase filter. Such systems allow resampling by arbitrary ratios while simultaneously performing baseband aliasing from center frequencies at Nyquist zones that are not multiples of the output sample rate. A non-maximally decimated polyphase filter bank, where the number of data loads is not equal to the number of M subfilters, processes M subfilters in a time period that is either less than or greater than the M data-load's time period. We present a load-process architecture (LPA) and a runtime architecture (RA) (based on serial polyphase structure) which have different scheduling. In LPA, N subfilters are loaded, and then M subfilters are processed at a clock rate that is a multiple of the input data rate. This is necessary to meet the output time constraint of the down-sampled data. In RA, M subfilters processes are efficiently scheduled within N data-load time while simultaneously loading N subfilters. This requires reduced clock rates compared with LPA, and potentially less power is consumed. A polyphase filter bank that uses different resampling factors for maximally decimated, under-decimated, over-decimated, and combined up- and down-sampled scenarios is used as a case study, and an analysis of area, time, and power for their FPGA architectures is given. For resource-optimized SDR front-ends, RA is superior for reducing operating clock rates and dynamic power consumption. RA is also superior for reducing area resources, except when indices are pre-stored in LUTs. | Mehmood Awan Yannick Le Moullec Peter Koch Fred Harris | 2012 | ZTE Communications2012，10，1： | 3 |
| 3 | 变采样多相滤波器组信道化接收机的实现显示文摘针对多相滤波器组信道化接收机的通道采样率在数值上等于通道带宽,因此无法兼顾最优信道带宽和最优采样率的问题,提出一种基于嵌入式变采样多相滤波器组的信道化接收机。该信道化接收机根据要求的变采样率改变数据的输入速率,并依据数学推导对原有系统的结构进行变形,可有效解决多相滤波器组通道采样率和通道带宽的耦合问题,从而实现嵌入式变采样的目的。本接收机设计方法在兼顾系统最优采样和最小信道带宽要求的前提下,能有效避免频道浪费或复杂的插值算法。仿真结果表明,该接收机在不增加计算量的基础上能有效改变采样率,提高系统实时处理能力。 | 唐尧 李波 左晓亚 杨懋 闫中江 | 2018 | 雷达科学与技术2018，16，2： | 2 |
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