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| 1 | A high-accuracy DCO with hybrid architecture显示文摘In this paper, a novel hybrid digital-controlled oscillator(DCO) is proposed, which is used to improve the accuracy of the all-digital clock generator without reference source. The DCO with hybrid architecture consists of two parts: DCO_high and DCO_low. The DCO_high decides the coarse output frequency of DCO, and adopts the cascade structure to decrease the area. The DCO_low adopts the chain structure with three-state buffer, and decides the fine output frequency of DCO. Compared with traditional cascade DCO, the proposed hybrid DCO features higher precision with less inherent delay. Therefore the clock generator can tolerate process, voltage and temperature(PVT) variation and meet the needs of different conditions. The DCO is designed in SMIC 180 nm CMOS process with 0.021 mm^2 chip area. The output frequency is adjusted from 15–120 MHz. The frequency error is less than 0.83% at 25 MHz with 1.6–1.8 V supply voltage and 0–80℃ temperature variations in TT, FF,SS corners. | Yapeng Sun Huidong Zhao Shushan Qiao Yong Hei Fuhai Zhang | 2017 | Journal of Semiconductors2017，38，7： | 0 |
| 2 | Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate显示文摘Digital controlled oscillators(DCOs) are the core of all digital phase locked loop(ADPLL) circuits. Here,DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology.Three,four and five bit controlled DCO with NMOS,PMOS and NMOS & PMOS transistor switching networks are presented.A three-transistor XNOR gate has been used as the inverter which is used as the delay cell.Delay has been controlled digitally with a switch network of NMOS and PMOS transistors.The three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740μW.A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998μW.Output frequency and power consumption results for 4 & 6 bit DCO circuits with one PMOS and NMOS & PMOS switching network have also been presented.The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits.Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits. | Manoj Kumar Sandeep K.Arya Sujata Pandey | 2012 | Journal of Semiconductors2012，33，3： | 0 |
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