共被期刊论文引用了2次
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| 1 | REVIEW OF ADVANCED FPGA ARCHITECTURES AND TECHNOLOGIES显示文摘Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system integration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, interconnects, and embedded resources. Moreover, some important emerging design issues of FPGA architectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development. | Yang Haigang Zhang Jia Sun Jiabin Yu Le | 2014 | Journal of Electronics(China)2014，31，5： | 6 |
| 2 | Efficiently Exploring FPGA Design Space Based on Semi-Supervised Learning显示文摘Design space exploration(DSE) is an important step before the physical level design of Field programmable gate arrays(FPGA). An optimum architecture is usually selected from the whole space. As the architecture parameters increase, the huge time cost to explore an exponentially increasing space makes this method unrealistic. We propose a novel predictive modeling approach called ECOMT to estimate the area and delay of a circuit which is mapped onto an FPGA with certain architecture.Semi-supervised model tree is adopted to model the performance with respect to architecture parameters. Combined with nonlinear programming, the area and delay model obtained can be used to guide the DSE. Experimental results show that the model trained through ECOMT has Mean relative error(MRE) below 5% compared to VTR.Meanwhile the time used to attain the model is less than3 minutes, which reduces the time of DSE considerably. | YANG Liqun YANG Haigang LI Wei LI Zhihua | 2016 | Chinese Journal of Electronics2016，25，1： | 1 |
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