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452篇 您的检索式：期刊名="Very Large Scale Integration VLSI Systems IEEE Transactions on"

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	题名	作者	年代	出处	被引量
1	Rotmst Circuit and System Design Methodologies for Nanometer-Scale Devices and Single Electron Transistors 显示文摘	Alexandre Schmid Yusuf Leblebici	2004	IEEE Transactions on Very Large Scale Integration (VLSI) Systems2004，12，11：	1
2	Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints 显示文摘	Chen G Q Friedman E G	2006	IEEE Transactions on Very Large Scale Integration (VLSI) Systems2006，14，2：	1
3	Enhancement of fault injection techniques based on the modification of VHDL code 显示文摘	Baraza J C Gracia J Blanc S	2008	IEEE Transactions on Very Large Scale Integration (VLSI) Systems2008，16，6：	1
4	Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures显示文摘	Srinivasan V Govindarajan S Vemuri R	2001	IEEE Transactions on Very Large Scale Integration (VLSI) Systems2001，9，1：	1
5	A CORDIC processor for FFT computation and Its implementation using gallium arsenide technology显示文摘	Sarmiento R Tobajas F de Armas V	1998	IEEE Transactions on Very large Scale Integration VLSI) Systems1998，6，1：	1
6	Detecting,Diagnosing,and tolerating faults in SRAM-based field programmable gate arrays:a survey显示文摘	Doumar A Hideo I	2003	IEEE Transactions On Very Large Scale Integration(VLSI) Systems2003，11，3：	1
7	A survey of power estimation techniques in VLSI circuits 显示文摘	Najm F N	1994	IEEE Transactions on Very Large Scale Integration (VLSI) Systems1994，2，4：	1
8	Novel bio-inspired approach for fault-tolerant VLSI systems 显示文摘	Samie M Dragffy G Tyrrell A M	2012	IEEE Transactions on Very Large Scale Integration (VLSI) Systems2012，21，10：	1
9	Formal verification of architectural power intent显示文摘	HAZRA A GOYAL S DASGUPTA P	2013	Very Large Scale Integration (VLSI) Systems IEEE Transactions on2013，21，1：	1
10	Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified booth's algorithm显示文摘	J-H Hong C-W Wu	2003	IEEE Transactions on Very Large Scale Integration(VLSI)Systems2003，11，3：	1
11	BilRC: an execution triggered coarse grained reconfigurable architecture显示文摘	Atak O and Atalar A	2012	IEEE Transactions on Very Large Scale Integration ( VLSI) Systems2012，21，7：	1
12	High-efficiency multiple-output DC-DC conversion for low-voltage systems显示文摘	Dancy A P Amirtharajah R Chandrakasan A P	2000	Very Large Scale Integration IEEE Transactions on (VLSI) Systems2000，8，3：	1
13	A Survey of Design Techniques for System-Level Dynamic Power Management 显示文摘	Luca Benini Alessandro Bogliolo	2000	IEEE Transactions on Very Large Scale Integration (VLSI) Systems2000，8，3：	1
14	A sub-1 V,26 W,low-output-impedance CMOS bandgap refer-ence with a low dropout or source follower mode显示文摘	Ng D C W Kwong D K K Wong N	2011	IEEE Transactions on Very Large Scale Integration(VLSI) Systems2011，19，7：	1
15	Architectures for dynamic data scaling in 2/4/8K pipeline FFT cores显示文摘	LENART T OWALL V	2006	IEEE Transactions on Very Large Scale Integration (VLSI) Systems2006，14，11：	1
16	High Performance Low Power Array Multiplier Using Temporal Tiling显示文摘	Shivaling S M Poras T B	1999	IEEE Transactions on Very Large Scale Integration (VLSI) Systems1999，7，1：	1
17	High-performance energy-efficient D-flip-flop circuits显示文摘	KO U BALSARA P T	2000	IEEE Transaction on Very Large Scale Integration (VLSI) Systems2000，8，1：	1
18	An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques 显示文摘	JORG H ROLF E	2001	IEEE Transactions on Very Large Scale Integration (VLSI) Systems2001，9，2：	1
19	Design techniques and test methodology for low - power TCAMs 显示文摘	N Mohan W Fung D Wright M Sachdev	2006	IEEE Transactions on Very Large Scale Integration (VLSI) Systems2006，14，6：	1
20	VLSI architecture for layered decoding of QC-LDPC codes with high circulant weight显示文摘	SUN Yang and CAVALLARO J R	2013	IEEE Transactions on Very Large Scale Integration (VLSI) Systems2013，21，10：	1

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