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130篇 您的检索式：期刊名="IEEE Trans on VLSI System"

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	题名	作者	年代	出处	被引量
1	High-level synthesis of recoverable VLSI microarchitectures显示文摘	D M Blough F J Kurdahi Seong Yong Ohm	1999	IEEE Trans on VLSI Systems1999，7，4：	1
2	A survey of design techniques for system-level dynamic power management 显示文摘	Benini L Bogliolo A Micheli G D	2000	IEEE Trans on Very Large Scale Integration (VLSI) Systems2000，8，3：	1
3	Predictive system shutdown and other architectural techniques for energy efficient programmable computation 显示文摘	Srivastava M B Chandrakasan A P Brodersen R W	1996	IEEE Trans on Very Large Scale Integration (VLSI) Systems1996，4，1：	1
4	Predictive system shutdown and other architectural techniques for energy efficient programmable computation 显示文摘	SRIVASTAVA M CHANDRAKASAN A BRODERSEN R	1996	IEEE Trans on VLSI Systems1996，，1：	1
5	Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding显示文摘	Lin C H Chen C Y Wu A Y	2011	IEEE Trans on VLSI Systems2011，19，2：	1
6	A survey of power estimation techniques in VLSI circuits显示文摘	F N Najm	1994	IEEE Trans on VLSI Systems1994，2，4：	1
7	A Monte-Carlo approach for power estimation显示文摘	R Burch F Najm	1993	IEEE Trans on VLSI Systems1993，1，1：	1
8	Using magnetic RAM to build low power and soft error-resilient L1 cache 显示文摘	Sun Hongbin Liu Chuanyin Xu Wei	2012	IEEE Trans on Very Large Scale Integration (VLSI) Systems2012，20，1：	1
9	A Fully Pipelined Architecture for The LOCO-I Compression Algrithm显示文摘	Merlino P Abramo A	2009	IEEE Trans on Very Large Scale Integration (VLSI) Systems2009，17，7：	1
10	An on-chip march pattern generator for testing embedded memory cores显示文摘	WANG Wei-Lun LEE Kuen-Jong WANG Jging-Fa	2001	IEEE Trans on VLSI Systems2001，9，5：	1
11	Small area parallel Chien search architecture for long BCH codes显示文摘	CHEN Yan-ni PARHI K K	2004	IEEE Trans on very large scale integration (VLSI) systems2004，，：	1
12	Area-efficient High-speed Decoding Schemes for Turbo Decoders显示文摘	Wang Z Chi Z Parhi K K	2002	IEEE Trans on VLSI Systems2002，10，6：	1
13	A survey of design techniques for system 显示文摘	BENINI L BOGLILO A MICHELI G	2000	IEEE Trans on VLSI systems2000，8，3：	1
14	Circuit and microarchitectura] techniques for reducing cache leakage power 显示文摘	N S Kim K Flautner D BBlaauw	2004	IEEE Trans on VLSI Systems2004，12，2：	1
15	A framework for reconfigurable computing task scheduling and context management显示文摘	MAESTRE R KURDAHI F FERNANDEZ F	2001	IEEE Trans on VLSI Systems2001，9，6：	1
16	On Area/Depth Trade-Off in LUT-Based FPGA Technology Mapping显示文摘	Cing J Ding Y	1994	IEEE Trans on VLSI Systems1994，2，2：	1
17	Ant colony system application to macrocell overlap removal显示文摘	ALUPOAEI S KATKOORI S	2004	IEEE Trans on Very Large Scale Integration ( VLSI ) Systems2004，12，10：	1
18	Two new techniques integrated for energy- efficient TLB design显示文摘	CHANG Y J LAN M F	2007	IEEE Trans on Very Large Scale Inte- gration ( VLSI ) Systems2007，15，1：	1
19	Compiler assisted STT-RAM based hybrid cache for energy efficient embedded systems 显示文摘	Li Qingau Li Jianhua Shi Liang	2014	IEEE Trans on Very Large Scale Integration (VLSI) Systems2014，22，8：	1
20	Implementation of a CMOS LNA plus mixer for GPS applications with no external components显示文摘		2001	IEEE Trans on VLSI Systems2001，9，1：	1

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