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119篇 您的检索式：期刊名="IEEE Trans Very large scale integration systems"

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	题名	作者	年代	出处	被引量
1	Detecting,diagnosing,and tolerating faults in SRAM-based field programmable gate arrays:A survey显示文摘	Doumar A Ito H	2003	IEEE Trans on Very Large Scale Integration Systems2003，11，3：	1
2	Testing configurable LUT-based FPGA' s显示文摘	Huang W K Meyer F J Chen X T	1998	IEEE Trans on Very Large Scale Integration Systems1998，6，2：	1
3	Nonlinear multi-error correction codes for reliable MLC NAND flash memories显示文摘	Wang Z Karpovsky M Joshi A	2012	IEEE Trans on Very Large Scale Integration Systems2012，20，7：	1
4	A high-performance unified-field reconfigurable cryptographic processor显示文摘	Chen J H Shieh M D Lin W C	2010	IEEE Trans on Very Large Scale Integration Systems2010，18，8：	1
5	A survey of design techniques for system-level dynamic power management 显示文摘	Benini L Bogliolo A Micheli G D	2000	IEEE Trans on Very Large Scale Integration (VLSI) Systems2000，8，3：	1
6	Precomputation-based sequential logic optimization for low power显示文摘	MAZHAR A JOSE M DEVADAS S	1994	IEEE Trans Very Large Scale Integration Systems1994，2，4：	1
7	Predictive system shutdown and other architectural techniques for energy efficient programmable computation 显示文摘	Srivastava M B Chandrakasan A P Brodersen R W	1996	IEEE Trans on Very Large Scale Integration (VLSI) Systems1996，4，1：	1
8	The effect of LUT and cluster size on deep Submicron FPGA performance and density 显示文摘	Ahmed E Rose J	2004	IEEE Trans Very Large Scale Integration (VLSI)Systems2004，12，3：	1
9	High-speed architectures for parallel long BCH encoders显示文摘	Zhang Xinmiao Parhi K K	2005	IEEE Trans on Very Large Scale Integration Systems2005，13，：	1
10	A reconfigurable multifunction computing cache architecture显示文摘	KIM H SOMANI A K TYAGI A	2001	IEEE Trans on Very Large Scale Integration Systems2001，9，4：	1
11	Using magnetic RAM to build low power and soft error-resilient L1 cache 显示文摘	Sun Hongbin Liu Chuanyin Xu Wei	2012	IEEE Trans on Very Large Scale Integration (VLSI) Systems2012，20，1：	1
12	A Fully Pipelined Architecture for The LOCO-I Compression Algrithm显示文摘	Merlino P Abramo A	2009	IEEE Trans on Very Large Scale Integration (VLSI) Systems2009，17，7：	1
13	Ultralow-voltage process-variation-tolerant schmitt-trigger-based SRAM design显示文摘	Kulkarni J P Roy K	2012	IEEE Trans on Very Large Scale Integration Systems2012，20，2：	1
14	Small area parallel Chien search architecture for long BCH codes显示文摘	CHEN Yan-ni PARHI K K	2004	IEEE Trans on very large scale integration (VLSI) systems2004，，：	1
15	Low-power scan design using first-level supply gating显示文摘	S Bhunia H Mahmoodi D Ghosh	2005	IEEE Trans on Very Large Scale Integration Systems2005，13，3：	1
16	Leakage current reduction in CMOS VLSI circuits by input vector control显示文摘	A Abdollahi F Fallah M Pedram	2004	IEEE Trans on Very Large Scale Integration Systems2004，12，2：	1
17	Ant colony system application to macrocell overlap removal显示文摘	ALUPOAEI S KATKOORI S	2004	IEEE Trans on Very Large Scale Integration ( VLSI ) Systems2004，12，10：	1
18	The design of a SRmM-based field-programmable gate array, Part Ⅱ: circuit design and layout 显示文摘	CHOW P SEO S O ROSE J	1999	IEEE Trans Very Large Scale Integration Systems1999，7，3：	1
19	C-Pack:a high-performance microprocessor cache compression algorithm显示文摘	CHEN Xi YANG Lei DICK R P	2010	IEEE Trans on Very Large Scale Integration Systems2010，18，8：	1
20	Compiler assisted STT-RAM based hybrid cache for energy efficient embedded systems 显示文摘	Li Qingau Li Jianhua Shi Liang	2014	IEEE Trans on Very Large Scale Integration (VLSI) Systems2014，22，8：	1

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